Deadlock-Free Verification of the SACI-1 OBC Using Circus Time Action and FDR

Formal Specification and Validation of Computer Systems is an important development methodology in software engineering, especially in life-critical systems. Formal software development involves the use of formal specification languages to specify the system behavior and the implementation of the specification. Model checking tools and theorem proving tools can be used to validate if the system implementation satisfies the specification or, to explore specific characteristics such as liveness and deadlock free. Circus Time Action (CTA) is a formal specification language developed to add time related observations to the semantic model of Circus family of formal specification languages. A mapping between Circus semantic model, based on Unified Theories of Programming (UTP), and CTA semantic model exists. Such mapping permits a sound syntax mapping from CTA to the original Circus syntax. Additionally, a framework for validating the untimed properties of CTA has been created, enabling the validation of specifications properties written in CTA using a variety of model checking techniques and, therefore, including Failures Divergence Refinement (FDR). In the present work, we explored the use of such a framework by applying it to a case study. We used CTA to specify the implementation of First Brazilian Scientific Application Satellite (SACI-1) On-Board Computer (OBC). Further, we applied the mapping between Circus Time Action and Circus to obtain an untimed specification of the SACI1-OBC. FDR is used to check for deadlock-free property of the SACI1-OBC specification. The obtained results were fully consistent with the previous similar work of SACI-1-OBC.