Influence of High-frequency Power Loop Inductance on GaN-based Neutral-Point-Less X-type (NPL.X) Three-level Inverter

In response to the growing need for high-power inverters and drives with superior power density, efficiency, and reliability, wide bandgap (WBG)-based multilevel inverters (MLIs) are gaining prominence. However, incorporating WBG devices into conventional neutral-point-clamped (NPC) MLIs presents notable challenges, mainly due to their high dv/dt and multiple minor power loops through the neutral point connection. These issues lead to voltage unbalances among the switches and capacitors and increased voltage overshoots in the devices, leading to premature component failures. Recently, a neutral-point-less Xtype (NPL.X) three-level inverter has been proposed that does not require a split dc-link capacitor and neutral point connection. The removal of neutral point connections eliminates unnecessary minor power loops, leading to minimal high-frequency (HF) power loop inductance. This paper investigates the influence of HF power loop inductance on the NPL.X in comparison with the conventional three-level NPC inverter. The preliminary simulation and analytical study reveal that NPL.X can effectively reduce voltage unbalances and voltage overshoot by 77% and 42%, respectively, compared to the NPC inverter. In addition, 38% reduction in output voltage undershoot has been achieved by the proposed NPL.X.