A General Approach for Maximizing Heat Transfer and Minimizing Capacitance Between MOSFET Configuration and Heat Sink with Thermal Pads

Heat sinks, in conjunction with thermal pads, limit MOSFET exposure to inoperable thermal conditions in power electronic applications; allowing an expansion in their range and operation. While heat sinks used this way are commonplace in power electronics and largely beneficial, their hardware application adds parasitic capacitance between the drain of the FETs. Thus, it can be assumed that this would create residual interference and electrical losses between the FET and heat sink. This paper seeks to provide an accurate measure of this capacitance, calculate power lost in our application, and determine an optimal thermal pad thickness to minimize our results.