A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS

This brief presents a 16-bit 5 GS/s current-steering digital-to-analog converter (DAC) with a redundant-MSB based digital pre-distortion (RMDPD) technique. 1-bit MSB is added during decoding to accommodate digital compensation of element mismatch errors, enhancing both the low-frequency and high-frequency linearity without penalty on the noise floor. In addition, an improved data/dummy-data scheme, which incorporates the dummy-data generation logic into the 2:1 multiplexer (MUX) with half-rate clock, is used to mitigate the code-dependent supply ripples and induced retiming errors. The implemented DAC achieves > 61 dBc spurious-free dynamic range (SFDR) and < −72 dBc third-order intermodulation distortion (IM3) for output frequencies up to Nyquist. The DAC core occupies $0.42~mm^{2}$ active area and dissipates about 360 mW at 1.8V/1.0V/-1.8V supply.