Area- and Power-Efficient Compute-in-Memory Macro Based on Oxide Semiconductor 2T0C eDRAM With Cell-System Co-Optimization

In this work, we propose a high-density energy-efficient compute-in-memory (CiM) macro design for edged AI applications based on long retention 2T0C eDRAM cells using oxide semiconductor transistors. The design adopts a mixed-mode (digital storage/analog computing) strategy with multiple weight states and differential pair design for area-efficient multiply-accumulate (MAC) operation with robustness to process-induced variation. This design also enables the development of a cell-system co-optimization method to maximize the area and power efficiency. As a result, when projected to a 10-nm channel length, the CiM macro achieves an energy efficiency of >3330 TOPs/W and area efficiency of 57.34 TOPS/mm2, which is superior to the reported SRAM or eDRAM CiM technologies.