Vertical-Channel Fin-SiC (VC Fin-SiC) With Partially Highly Doped JFET for 3.3-kV Applications

To develop a 3.3-kV 4H-silicon carbide (SiC) MOSFET with high efficiency and reliability, we explored a new structure, the vertical-channel Fin-SiC (VC Fin-SiC) as a 3.3-kV SiC MOSFET device. While VC Fin-SiC has been developed and already shown excellent properties, we found that there is still room for reducing resistance while maintaining reliability. According to TCAD simulations, VC Fin-SiC shows a bottleneck region that limits the reduction of on-resistance. To address this bottleneck, the introduction of a partially highly doped JFET is proposed. In an evaluation of electric characteristics, the developed VC Fin-SiC showed a better tradeoff between on-resistance (R
$_{\text {on}})$
and electric field strength in the gate oxide (E
$_{\text {ox}})$
compared with a VC Fin-SiC without a partially highly doped region in the JFET, that is, a 9% lower Ron and 0.17 MV/cm lower Eox. In addition, the developed VC Fin-SiC has a short-circuit (SC) capability of
$3.9~\mu $
s. These notable features enable better efficiency and reliability for 3.3-kV SiC MOSFETs while taking advantage of the novel structure of VC Fin-SiC.