PSyGS Gen A Generator of Domain-Specific Architectures to Accelerate Sparse Linear System Resolution

Sparse linear system resolution is a crucial task in scientific computing. The symmetric Gauss-Seidel algorithm (GS) is an efficient iterative resolution method. However, its inherently sequential nature makes it challenging to parallelize. The state-of-the-art parallelization techniques for the GS iteration are based on the concept of graph coloring, and they have been exploited to speed up the execution of each iteration of the algorithm on CPUs, e.g., in the context of the HPCG benchmark. Nevertheless, existing hardware accelerators for GS execute the serial algorithm, often tailoring it to a specific application scenario, limiting its applicability. We propose a hardware-software codesign methodology that leverages state-of-the-art software graph coloring and a generator of domain specific architectures (DSAs) that computes GS using coloring-based hardware parallelization. PSyGS Gen (Parallel Symmetric Gauss-Seidel Generator) is the first architecture to parallelize the Gauss-Seidel iteration via graph coloring. By comparing the performance of the DSAs generated by PSyGS Gen to a parallelized version of the algorithm implemented using coloring and OpenMP and run on a CPU, we achieve from 1.23x to 34.84x higher parallel efficiency than the best CPU run. The DSAs generated using PSyGS Gen are programmable, therefore, they support any present and future coloring techniques. Moreover, they also support the execution of the algorithm for a fixed number of iterations, allowing its usage as a smoother in more complex iterative methods. These programmability features, with the solution being open-source and integrated with the Chipyard SoC generator, allow it to be integrated into more complex flows of computation such as the HPCG benchmark.