Integration Framework for Online Thread Throttling with Thread and Page Mapping on NUMA Systems

Non-Uniform Memory Access (NUMA) systems are preva-lent in HPC, where optimal thread and page placement are crucial for enhancing performance and minimizing energy us-age [1]–[3]. Moreover, considering that NUMA systems have hardware support for a large number of hardware threads and many parallel applications have limited scalability, throttling the number of active threads may bring further improvements [4]–[6]. However, the optimal configuration (thread mapping, page mapping, number of threads) for energy and performance, quantified by the Energy-Delay Product (EDP), varies with the system hardware, application, input set, and even during execution [1], [4], [6], [7]. Only online optimization approaches can easily adapt to these changes.