ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping

We present ConvMap: an RTL-based framework that utilizes specific mapping techniques to FPGA resources to achieve an improved throughput for convolution (Conv) operations. Our approach maps the convolution operation onto efficient pipelined DSP-adder tree (PDAT) structures combined with a serial-in serial-out (SISO) buffer. We implement the Conv layer on AMD-Xilinx Ultra96 FPGA. We demonstrate 2.4x frequency improvement and 14x-20x reduction in LUT utilization on the FPGA. Leveraging tiled PDATs with hybrid LUT/DSP usage, we achieve a competitive peak throughput of 544 GOP/s.