Graph Computing on Long Vector Architectures (Yes, It Works!)

The HPC market is witnessing the appearance of emerging architectures exploiting long and variable vector lengths, like the NEC SX-Aurora or the RISC-V vector extension. These new architectures often require rethinking scientific algorithms to leverage their potential, and sparse computations can be the most challenging codes to adapt. Specifically, we showcase the obstacles of vectorizing graph algorithms and propose a graph representation suited for long vector architectures. We evaluate our work implementing three graph algorithms, Breadth-First-Search (BFS), Connected Components (CC), and Page Rank (PR), for a prototype RISC-V core with a long Vector Unit, presenting optimizations that benefit long vector architectures. We also run our implementations on the NEC SX-Aurora and compare our results with other graph libraries for CPUs and vector acceleration. Our BFS and CC implementations outperform CPU approaches by a factor around 4× depending on the algorithm and graph, with PR having a speedup closer to 20×. We also match or outperform the single-core performance of other vector implementations in the NEC SX-Aurora by 2× on average. We exhibit the efficiency of the RISC-V prototype, obtaining more performance out of its available bandwidth than the other evaluated single-core architectures. More generally, we show that adapting data structures and algorithms unleashes the potential of long vector architectures for sparse computations, demonstrating that these emerging technologies strive against traditional accelerated computing.