A Runtime Manager Integrated Emulation Environment for Heterogeneous SoC Design with RISC-V Cores

RISC-V based architectures have gained attention for deployment on platforms from SoC to HPC scale to meet the demands of a wide range of computational workloads that may require specialized hardware tailored to their specific performance goals. In previous works, we introduced CEDR, an open-source, unified compilation and runtime framework designed to facilitate productive hardware-agnostic application deployment on heterogeneous architectures, and lift the barriers to research on the design and evaluation of scheduling heuristics and accelerators for heterogeneous systems. In this study, we demonstrate the capability of CEDR in supporting heterogeneous systems composed of RISC-V cores and a pool of accelerators. We investigate the impact of employing customized lightweight RISC-V cores for managing accelerators individually. Such management approach, compared to centralized accelerator management model, scales down the stress on the runtime environment where compute resources are shared among multiple applications each with varying degrees of task-level parallelism. We perform evaluations on a heterogeneous SoC emulated on the Xilinx Virtex-7 FPGA based on execution of applications from radar, signal processing, and autonomous vehicles domains. We observe that releasing CPU-based compute cores from accelerator management through lightweight RISC-V cores results with up to 47% reduction in time spent on accelerator management. Since CPU-based compute cores exclusively become available for application task execution and contention on resource management is reduced, we observe speedup of up to 2.2x in application execution time based on experiments conducted with workloads consisting of dynamically arriving real-life application scenarios.