Effect of Line Resistance of Passive Memristive Crossbars on Spiking Neural Network Performance

Hardware spiking neural networks using memristors as synapses are promising candidates for highly integrated and low-power event-based computations. However, when using passive synaptic crossbars, a number of limitations linked to the high parallelism of the memristive synapses appear. In this paper, we focus on the detrimental effect of the synaptic line resistance of passive crossbars made of ferroelectric tunnel junction memristive devices on learning capabilities. Using a model of such memristive device that considers the actual voltage applied on the synapses when updating their weights, we show how this line resistance impacts the performance of a single layer all-to-all spiking neural network using unsupervised and reward-modulated learning, and how these detrimental effects can be mitigated.