The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices

A multiple-layer network implementation with an array of static-random-access-memory (SRAM) based reconfigurable cognitive computation matrices (RCCMs) is presented. The multiply-accumulation output currents can be converted into single-ended currents by on-chip analog nonlinear circuits to realize three commonly used activation functions: the rectified linear unit (ReLU), radial basis function (RBF), and sigmoid function. The resultant output currents from the RCCM are designed to either broadcast to other RCCMs in voltage mode or be summed up in current mode. A concept-proving prototype chip, including a 17×16 RCCM with 4-bit input and weight resolutions, has been designed and fabricated in a 0.18µm CMOS process. The measured computation efficiency is 3.6TOPS/W. The computation accuracy deteriorated by process variation can be significantly improved by adopting 49 mismatch parameters after calibration. A handwritten digit recognition database, MNIST, is employed to evaluate the chip performance by implementing a 3-layer neural network, achieving an accuracy of 91.2%.