TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning

Temporal Neural Networks (TNNs), a special class of spiking neural networks (SNNs), process information via spike timings, analogous to the brain. Recent works have proposed microarchitecture and custom macros for directly implementing extremely energy-efficient TNNs with standard CMOS. However, prior works implement synapses using expensive register-based counters. Since synapses constitute most of the hardware complexity in TNNs, it is imperative to optimize their implementation. This work proposes TNN-CIM, an in-SRAM implementation of synaptic arrays, as a first attempt towards compute-in-memory (CIM) solution for TNNs. In TNN-CIM, not only are the synaptic weights stored in SRAM, but synaptic response function generation (inference) and spike timing dependent plasticity (learning) are also embedded directly within the SRAM array. Our results in 45nm CMOS demonstrate 1.3x and 1.7x reduction in power and area respectively while improving latency performance by 1.4x. Further, we provide transistor count equations to assess hardware complexity scaling of arbitrary TNN-CIM synaptic arrays.