Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators

Energy-efficient artificial intelligence (AI) accelerator designs with analog multiply-accumulate (MAC) cells as a key computation element have emerged to meet the demand for executing AI applications on edge devices. In this paper, we characterize an energy-efficient MAC cell with an analog two-quadrant multiplier and a dynamic analog multi-bit weight memory by measurements. It is designed and fabricated in a 22nm FD-SOI CMOS technology. The experimental results confirm the operating principle of the analog MAC cell and demonstrate its advanced performance.