An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA

In view of the demanding computational requirements and constraints on accuracy, the development of an accurate and energy-efficient accelerator for single-image super-resolution is a substantial challenge. This paper introduces a feature retrieval method based on high parallel memory access, which outputs the trained network’s feature values to replace intensive computation and improving the energy efficiency in hardware system. Firstly, we train a cascaded-parallel convolutional network by combining multiple receptive field (RF) shapes in order to optimize recovery accuracy. Then transferring the output features of the trained model to the memory units. Following this, the accelerator is designed based on a highly parallel memory access mechanism, and the features stored in the output memory units are retrieved, thereby circumventing a substantial number of convolution operations. Comprehensive experiments demonstrate that the proposed method achieves competitive recovery accuracy and frame rate when compared with deep neural network (DNN) methods on 3 widely used benchmarks, while also attaining an exceptional energy efficiency of 347.2 Mpixels/J.