Efficient Hardware Implementation of Artificial Neural Networks on FPGA

A neural network finds widespread applications across various domains, with the primary challenge being the design of a network characterized by low area and power consumption. This paper introduces an efficient design strategy for a cost-effective neural network architecture. It leverages a shared multiplier and accumulator arrangement between neighboring nodes, halving the number of these units and subsequently reducing the overall area of the neural network. A configuration mechanism is employed to synchronize the operation between the two common nodes. The proposed method is implemented and tested using VHDL on an Altera 10 GX FPGA, and evaluations include testing with two datasets: MNIST and CIFAR-10. The results demonstrate that the proposed method maintains classification accuracy while achieving a 76% reduction in area compared to traditional methods, with a power consumption of 82 mW. These findings underscore the efficiency and suitability of the proposed method for applications prioritizing both area and energy efficiency.