An 11T1C Bit-Level-Sparsity-Aware Computing-in-Memory Macro With Adaptive Conversion Time and Computation Voltage

A static random-access memory (SRAM)-based computing-in-memory (CiM) is a promising architecture for efficiently performing high-precision integer (INT) multiplication and accumulation (MAC) operations. In this work, we propose a charge-domain bit-level-sparsity-aware analog CiM (ACiM) macro for an area-energy-efficient convolutional neural network (CNN). An 11T1C ACiM bit-cell is proposed to dynamically remove the computation capacitors during the accumulation phase based on the weight value (W) for improving the partial sums and analog computing accuracy margin (ACAM). The computation voltage is dynamically adjusted according to column-wise sparsity by the bit-level-sparsity-aware controller to improve energy efficiency. To digitize the MAC computing results, a 2-8bit column-parallel time-interleaved hybrid analog-to-digital converter (ADC) is designed by sharing the voltage reference generator, which achieves a low unit pitch size. A 256
$\times$
64 11T1C ACiM macro prototype with hybrid ADCs is implemented using 55nm CMOS process. The silicon measurement results show that the proposed ACiM achieves a throughput of 51.2-153.6 GOPS, core area efficiency reaching 112-336GOPS/mm
$^{2}$
, and energy efficiency ranging from 17 to 111 TOPS/W with 8bit weights and 8bit inputs.