A Convolutional Neural Network Accelerator with High-level Synthesis

The use of hardware description languages (HDLs) and the implementation of techniques like pipelining and dataflow optimization significantly increase the complexity of designing field-programmable gate arrays (FPGAs). This added complexity poses challenges in translating hardware descriptive code into FPGA-recognizable bitstreams. Despite high-level synthesis (HLS) facilitating the translation of C or C++ into HDL and enhancing deployment efficiency, current HLS optimization schemes remain limited, necessitating complex processes and prolonged simulation times. Addressing these challenges, we propose an HLS-based convolutional neural network (CNN) accelerator that constructs various CNN models, including convolutional and pooling modules, using the C language and optimizes resource utilization via diverse HLS directives. Resource utilization is subsequently visualized through simulation and synthesis. Conducting experiments with Vitis 2021.1, our accelerator effectively converts the C-constructed CNN into HDL, markedly reducing resource utilization metrics such as lookup tables and latency.