Design and Optimization of a High-Efficiency CML Frequency Divider in InP DHBT Technology with Maximized Self-Oscillation Frequency

This paper reports on the design and experimental validation of a high-efficiency current-mode logic (CML) frequency divider in a 0.25-m indium phosphide double-heterojunction bipolar transistor (InP DHBT) process. The proposed divider is designed to operate over a wide frequency range of 20–40 GHz, with a focus on maximizing the self-oscillation frequency (SOF) and the ratio of SOF to the transistor cutoff frequency (fT). To achieve this goal, we employ theoretical design models and circuit simulations to optimize the device sizing, biasing, and layout parasitics. We also perform a comprehensive experimental characterization of the fabricated divider under various input frequencies and power levels. The measurement results show that the divider achieves a high SOF of 43.2 GHz and a high fT utilization of 86%, demonstrating the effectiveness of our design methodology.