FPGA Implementation and Optimization of Adder Performance with Hybrid FinFET-GDI Logic

This study proposes a novel approach that combines a hybrid FinFET-Gate Diffusion Input (GDI) logic to create a Carry Select Adder (CSLA) architecture on Field-Programmable Gate Arrays (FPGAs). Carry Select Adders are crucial parts of digital signal processing and frequently demand for excellent performance. But Carry Select Adder's traditional FPGA implementation often uses a lot of power, which makes it impractical to use them in situations when power is limited. In order to address this issue, we provide a design approach that leverages the benefits of FinFET-GDI and CSLA logic. The CSLA architecture provides fast operation, while the FinFET-GDI logic reduces power consumption by making effective use of transistors. We are able to develop a low-power Carry Select Adder that is appropriate for FPGA systems by combining these strategies. Tanner synthesis and implementation demonstrate the effectiveness of the suggested design, demonstrating significant power savings while maintaining critical performance metrics such as time and delay. In conclusion, the SPARTAN 3E Kit was used to construct the hardware for the suggested low-power Carry Select Adder. The Tanner tool was used to conduct simulations, which made it possible to thoroughly analyze and validate the design. Moreover, Xilinx software was utilized to extract netlists and thoroughly verify them, guaranteeing the accuracy and stability of the implementation. The Power consumption in adders is reduced by 17%, our technique shows promise for low-power embedded signal processing applications, since experimental results show significant power reductions over previous approaches.