Design of High-Speed Wideband Digital Upconverter

The paper proposes a high-speed wideband digital upconverter circuit (DUC) design method, utilizing an optimized CORDIC algorithm to implement a numerically controlled oscillator (NCO) and a four-stage cascade parallel-folded half-band filter (HB-FIR) for interpolation sampling and filtering. Additionally, digital mixing is used to modulate the baseband signal. In the implementation of the circuit design, multi-channel parallel and multiplexing techniques are utilized to reduce hardware costs and power consumption. The final hardware code design for the DUC circuit is completed, with a total area of
$550.\overline{1}6^{*}550_{\mathrm{I}^{1}}\mathrm{m}_{9}^{2}$
about 234609 instances, using the
$28\text{nm}$
process. The single-channel working frequency can reach
$825\text{MH}_{4}$
and with four channels of interleaved sampling, the maximum sampling rate can reach 3
$3\text{GHz}$