Hardware Acceleration Design of Convolutional Neural Networks Based on FPGA

In today's rapidly advancing technological landscape, the applications of deep learning permeate various facets of our lives. However, traditional implementations of convolutional neural networks (CNNs) on platforms such as CPUs and GPUs often require substantial network bandwidth and incur high power consumption. Deploying CNNs on Field-Programmable Gate Arrays (FPGAs) with efficient logic control from CPUs offers a promising solution for low-power and compact hardware designs. This paper proposes a novel approach to optimize YOLOv3-tiny on FPGA, aiming to reduce hardware resource consumption and power usage while enhancing the computational efficiency of the convolutional neural network. Through hardware optimization strategies, our solution demonstrates improved performance, making it well-suited for real-time deep learning inference tasks in resource-constrained environments.