Design and Implementation of 4 Bit Carry Generator Circuit Using Pass Transistor Logic with 2 × 1 Mux Approach

This study employs the pass transistor logic technique to design and implement Very Large-Scale Integration (VLSI) factors in the context of various adders. The area consumption, power consumption, and propagation latency of traditional adders, like Carry Lookahead Adders (CLA) and Ripple Carry Adders (RCA), are frequently problematic. The study investigates the use of the pass transistor logic technique in the design and construction of several adder circuits in order to overcome these issues. This method is well known for its ability to increase efficiency by providing lower power consumption and shorter signal propagation delays. Using 2 × 1 multiplexers in the adder circuits is a crucial part of this strategy. After that, the design stage entails creating modules that are especially suited for various adder configurations while taking into account the particular circumstances in which the carry input (Cin) is either 0 or 1. By selecting the right outputs according to the encoded state, 2 × 1 multiplexers-controlled bypass transistor logic simplify the total number of states the circuit has to handle. The project's goal is to improve adder circuit efficiency by in-depth research and testing, which will further VLSI design for digital circuits.