Low Power Approximate Ternary Multiplier Architecture for Image Processing Applications

Approximate computing is a developing technology that seeks to significantly enhance the speed, and power usage in image processing applications, particularly in cases where exact precision isn't necessary. This paper presents an energy-efficient approximate ternary full adder with CNTFET technology, which is used in the reduction stage in the implementation of a 6x6 approximate ternary multiplier. The proposed ternary full adder design has better performance than most of the existing designs in terms of speed and power, which exhibits an improvement in power upto 40%. The proposed approximate 6x6 multiplier design has power savage up to 51.76%. Further to verify the effectiveness of the proposed multiplier, it is validated in image processing applications.