Performance Evaluation of various CMOS designs for Signal Processing Applications

The signal processing module or system in establishing communication needs to be proficient to make it cost and quality-effective and this is possible by forecasting right from the bottom (sub-system) level design. To achieve the intended performance of the module (like IIR filter), the design constraints of the sub-system at its block level need to be explored in terms of area, power, or delay. So, to strengthen the IIR filter the internal blocks (like ADDER, MULTIPLIER, and Delay elements) need to be refined. Circuit topologies like Complementary Metal Oxide Semiconductors (CMOS) serve the purpose to a great extent, because of their low power consumption and robustness, but not in the modern era, as the CMOS for N input logic to realize, we need 2N transistors, which results in large area requirement i.e., the complexity of circuit increases with Fan-in. The alternative for static CMOS design came into the picture i.e., Clocked CMOS logic gates like pseudo, dynamic, and domino logic families. To increase the efficiency of the IIR filter, one can consider the transistor level schematics in the best alternate CMOS logic design style and build an adder, multiplier. Comparing all the alternative CMOS designs such as Pseudo, dynamic, domino, Enhanced NMOS, and depletion NMOS in terms of area, power, and delay. Possible to realize logic using NAND or NOR gates. The NAND gate is the most preferred universal gate because of its superior delay performance.