Implementation of Physical Coding Sublayer of PCIE 3.0

A computer bus called third-generation PCI Express is used to connect peripherals in PCs, servers, mobile devices, and other systems. The PCI Express 3.0 physical layer's sublayer is called PCS. Transmitter and receiver are this layer's main components. The 8b/10b encoder, serializer, and scrambler make up the transmitter. This scheme's main goal is to incorporate a clock into the transmitter channels' serial bit stream. Along with the serial data bit stream, there is no clock transmitted. This produces DC balance and removes EMI noise.The receiver has an 8b/10b decoder. The 8b/10b decoder uses buffering, De-serializier, and descrambler to provide 8b character and data/control signals.With this module, disparity error and decode error can be identified. A loopback signal is produced if there are anyerrors in the received data. In this study, the RTL code is simulated and implemented using the Questa sim tool. Verilog is used to represent several blocks of the physical coding sublayerof the physical layer for PCIe 3.0.