Infrastructure for Exploring SIMT Architecture in General-Purpose Processors

Single-Instruction Multiple-Thread (SIMT) computing has enabled a revolution in graphics, high-performance computing, and artificial intelligence. However, despite its benefits in these domains, SIMT processing has been relegated to accelerators rather than becoming a feature of general-purpose computing. Although a number of recent works have explored the potential benefits of “G PSIMT,“ current research infrastructures to study high performance general-purpose CPUs provide no support for the SIMT architecture and its programming model. This work presents our initial efforts toward developing a full-system GPSIMT research infrastructure. We first describe how we extend the QEMU emulator with SIMT features, enabling ISA pathfinding for GPSIMT hardware and providing a platform for the rapid development of system software for GPSIMT. We then present our approach to leveraging the Chip yard hardware gen-eration framework to develop a full-system GPSIMT exploration platform on an FPGA by extending the RISC- V Rocket Core.