On-Chip Learning of Neural Network Using Spin-Based Activation Function Nodes

Spintronic devices have been considered a promising candidate for the hardware implementation of neural networks (NNs) due to their potential to address the contemporary issue of power dissipation. Among these spintronic devices, spin-orbit torque (SOT)-based devices exhibit several advantages, including faster write speeds, longer endurance, and high energy efficiency in the implementation of NNs. In this work, on-chip learning of a fully connected NN (FCNN) for the Iris dataset is presented using an activation function leveraging SOT-magnetoresistive random access memory (SOT-MRAM) devices and two CMOS buffers. The proposed implementation achieves a testing accuracy of 98%. Furthermore, the results are compared with conventional CMOS-based tanh function, showing a 37.5%, 80.17%, and 93.84% improvement in latency, area, and energy for learning, respectively.