Engineering the breaking of topological protection in valley photonic crystals enables to design chip level functions for THz 6G communications and beyond

The realization of integrated, low-loss, and efficient systems for data-intensive applications such as augmented and virtual reality requires on-chip integrated photonic circuits, which have great potential for advanced information and communication technologies, including 6G wireless networks and intra- and inter-chip communication systems. A promising platform for achieving this revolution is Valley Photonic Crystals (VPCs). VPCs enable the construction of topological interfaces, which facilitate the propagation of light with minimal losses and backscattering through unidirectional edge modes. Interfacial topological interfaces and the degree of topological protection experienced by these robust edge modes is a relatively new perspective worth exploring. The ever-increasing demand for faster data rates in data-intensive applications like augmented and virtual reality necessitates the exploration of frequencies beyond the conventional 300 GHz band. In this study, we introduce variations in topological protection by considering different interfacial designs and suitable air-hole geometries for passive functional devices. We show that the partial breakup of topological protection can be an asset for the design of on-chip passive functionalities. We focus on bearded and zigzag junctions and appropriate air hole geometries for VPC unit cells. To experimentally verify the scalability of topological protection, we demonstrate the performance of terahertz (THz) topological ring resonators and THz double cavity resonators designed for operation in the 600 GHz frequency region. This work showcases how the scaling of topological protection can be achieved by utilizing a combination of air hole geometry and interfacial degrees of freedom, providing functional tuning of devices at the chip level.