Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC

This article presents a design methodology for compact single-channel 1 GS/s 8-bit 3-stage capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an information rate density (IRD) is mainly investigated in this work. With the proposed framework, an 8-bit prototype ADC reaches the highest IRD thanks to the optimum choice of DAC construction. To improve the performance of the ADC, we propose various circuit techniques such as 1) DC dependence compensation of charge-injection cell (ci-cell), 2) up-then-down DAC switching sequence, and 3) metastability detection to prevent the sparkle code error. The prototype ADC was fabricated in a 28-nm CMOS process and occupies an ultra-compact active area of 0.000261 mm
$^\text{2}$
, the smallest among the previously reported designs. At a 1.0 V supply voltage and 1 GS/s operation, the proposed ADC achieves an SNDR of 43.5 dB and dissipates 2.61 mW at the Nyquist rate, resulting in the state-of-the-art IRD of 470 TS/s
$\cdot$
conv/mm
$^\text{2}$
.