Advancements in Perceptron Hardware for Efficient Implementation in Artificial Neural Network

The quest for efficient hardware implementations of perceptrons in artificial neural networks (ANNs) is driven by the increasing demand for real-time processing and low-power computing. In the Master's thesis, the aim is to develop the hardware implementation of perceptron within a neural network. To do so, innovative hardware-based approaches are explored to optimize perceptron networks, focusing on enhancing accuracy, reliability, and fault tolerance while minimizing resource requirements and power consumption. The “Feedback Perceptron” introduces a transformative alteration to the per-ceptron's hardware architecture, elevating system accuracy by integrating a gain factor. The “Self-Healing Perceptron” proposes a fault-recovery mechanism, enhancing fault tolerance within the network. Both approaches aim to significantly improve accuracy, reliability, and fault tolerance while maintaining manageable hardware complexity. Implementation in Verilog HDL on the Xilinx Virtex-7 platform, using datasets like MNIST and Heart Attack-related data, demonstrates notable improvements in ac-curacy, showcasing the potential of these approaches to advance perceptron network capabilities.