Novel Power Grid Design Architecture to Improve IR Voltage Drop and EMI Shield

With technology shrinking and increasing functionality leading to high power consumption, today’s System-on-Chip (SoC) requires new power distribution network (PDN) design in BEOL layers to meet IR voltage drop. In the conventional approach, the PDN is designed with multiple metal and via layers which are very resistive and cannot support more than $\sim 2-3 A$ of current consumption with wire-bond packages with required IR voltage drop limit (e.g. $\lt 10 \%$). To support higher power consumption of SoC Applications, one needs to design with 3-4 dedicated thick metal layers of BEOL to design PDN in addition to a flip chip package which leads to higher wafer and package cost. For $16 \mathrm{~nm}$ and below technology nodes, Back-End-Of-Line (BEOL), Middle-Of-Line (MOL) and the package are becoming more critical in driving and shaping the chip and system level PPA (Power, Performance, Area) improvement. In this paper, two methods are proposed for novel power grid architecture design. One is fully-Platted-Power Grid (PPG) design and the other one is partially-Platted Power Grid (PPPG) design to improve IR voltage drop enabling higher chip power consumption and improving Electro-Magnetic Interference shielding (EMI Shield) using wire bond package to reduce wafer cost and package cost by avoiding flip chip package.