Circuit Model Construction for Simulating ESD Discharge Current Flowing through CMCs and ESD Suppression Devices

Electrostatic discharge (ESD) damage evaluation methods for common mode choke (CMC) and ESD suppression devices are standardized as IEC 62228-5 Annex E and Annex F, respectively. In this test, it is not possible to measure the current waveform flowing into the input section of the electronic device. Against this background, in this study, we investigated an equivalent circuit model that allows to know the discharge current waveform flowing into and through the CMC and ESD suppression device under test in advance using SPICE without performing measurements. Specifically, we examined the equivalent circuit model of the ESD gun and test board used in LTspice, and verified their validity by checking whether the voltage waveforms at the output of the test boards match the actual measurements. As a result, the model is valid to estimate the 1 st peak level and rise time of the discharge currents flowing through a CMC and the entire discharge current flowing through an ESD suppression device, within an error range of approximately $30 \%$.