A 131.5–137.5 GHz Low-Power Sub-Harmonic Receiver Using a 65-nm CMOS Technology

This paper presents a D-band low-power sub-harmonic receiver fabricated in a 65-nm CMOS technology. A sub-harmonic mixing technique is adopted to minimize the local oscillator (LO) leakage and to relax the design challenge of LO source. The receiver consists of a D-band differential low-noise amplifier (LNA), a D-band sub-harmonic mixer (SHM), a V-band frequency doubler, and an IF amplifier. The bias condition of the SHM is analyzed to draw the optimum LO swing for low dc power consumption. The LO signal is supplied by a frequency doubler with no additional drive amplifier. A charge injection technique is employed in the SHM to further reduce the dc power while keeping a high conversion gain and linearity. The receiver achieves a measured peak gain of 40.4 dB at 133.5 GHz and a 3-dB bandwidth of 6 GHz (131.5–137.5 GHz). The noise figure ranges from 12 to 17.2 dB over the 3-dB bandwidth, and the output 1-dB compression power is −1.8 dBm at 135 GHz. The total dc power consumption is as small as 77.4 mW. In addition, the receiver was tested with modulated signals, showing EVM of 7% with a 2-Gbaud/s 16-QAM signal and 4.9 % with a 1-Gbaud/s 64-QAM signal.