A Novel Digital Equalizer Based on RF Sampling Beyond GHz

Hardware implementations represent the major challenges when digital signal processors for ultra-wideband (UWB) signals must be developed. Due to the limitation of the maximum clock rate in digital devices, systems with high sampling rates (above GHz) cannot easily be implemented. In the literature, several works propose parallel architectures for the implementation of UWB. They are implemented on Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs) and try to overcome the limitation on the maximum clock frequency. In this work, a novel parallel architecture for digital UWB equalizer and an optimized version of the Least Mean Square Block (LMS) based on the Fast FIR Algorithms (FFA) are presented. Circuit simulations show that the proposed equalizer can process a UWB signal with a bandwidth reaching several GHz, using the typical clock frequencies available in FPGAs. The proposed version of the Block LMS is compared with the Fast Block LMS in terms of computational complexity. It exhibits better results and greater hardware design flexibility. Finally, the hardware implementation based on a Xilinx Kintex Ultrascale to process a UWB signal sampled at 1.6 GHz is described.