An Enhanced Harmonic Current Suppression Scheme for VSG Grid-Tied Operation

The slight distortion of the grid voltage will form a harmonic loop through the low harmonic impedance of the virtual synchronizer, causing distortion of the grid current. To address these problems, the existing harmonic current suppression schemes for virtual synchronous machines are based on the compensation of the harmonic voltage of the parallel network, which is limited by the line impedance and the size of the feedback gain, resulting in a limited harmonic suppression effect. In this paper, we propose a harmonic current suppression method for virtual synchronous machine with parallel branch and feedforward, which effectively improves the harmonic current suppression capability of virtual synchronous machine. By sampling the net-side output current of VSG, the proposed digital second-order fundamental trap is used to remove the fundamental component of the net-side current and feed forward to the input of the current inner loop of the virtual synchronous machine; at the same time, a parallel branch consisting of a second-order digital high-gain phase compensator is added to the current inner loop of the virtual synchronous machine, and the harmonic component in the input of the current inner loop of the virtual synchronous machine is fed forward for closed-loop control, thus This scheme achieves the suppression of harmonic currents on the network side of the virtual synchronous machine. Compared with the existing scheme, this scheme converts the open-loop suppression of harmonic currents common to the existing method into a more direct closed-loop control of harmonic currents, which is an effective way to realize the suppression of harmonic currents on the network side of the virtual synchronous machine.