FPGA Implementation of Light Weight Cryptography Using Extreme Low Power Reversible Dual Edge Triggered D Flip Flop

Addressing heat dissipation challenges in Very Large Scale Integration (VLSI) is pivotal, prompting exploration into in-novative solutions like reversible logic gate implementations. The primary goal is to enhance system security and power efficiency. Reversible Dual-Edge-Triggered Flip-Flops (RDETFFs) are employed to minimize power consumption, introducing unique data flow and synchronization approaches in digital electronics. The research delves into the flip-flop which trigger in dual edges, focusing on its role in digital sequential circuits. The objective extends to establishing a Light Weight Cryptography system with an Extreme Low Power RDETDFF,This project focuses on developing an Extreme Low Power RDETDFF for creating an energy-efficient Reversible Register (Rreg) and integrating en-cryption and decryption processes through a Reversible Register to strengthen cryptographic systems. Evaluation demonstrates significant performance improvement using reversible logic gates. Lightweight cryptography, designed for resource-constrained environments, prioritizes security without compromising efficiency. The entire program is implemented in Verilog for seamless integration and analysis, aligning with current technological needs and implementing in FPGA