Performance Analysis of Multiplier with Different Bits Size for MAC Unit

Cost, Energy, and Speed are some key important factors for all electronic circuits. We are trying to optimise these parameters in all electronic circuits. In the new era, the lower technology helps to reduce many problems in the area. Now the technology is at its peak. So coming up with a different algorithm for a design that reduces the power and delay will be effective in the market. Speed and power vary in importance according to the application. Multiplier is an important design for creating DSP, Filter, and MAC units. Creating a multiplier design that improves APD (Area, Power, Delay) will enhance the top-level logic performance. This paper compares and analyses the conventional multiplier, Vedic multiplier, and Wallace multiplier for 8,16, and 32-bit operations. The Vedic multiplier and Wallace multiplier provide a comparably equal performance. Even though the conventional multiplier provides a tight layout and easy implementation Wallace multiplier improves the power by more than 50% and delays considerably. Leveraging Verilog code, we simulate and synthesize the designs using Xilinx's Artix-7 AC701 Evaluation Platform.