A Novel SSD Buffer Design Based on STT-MRAM

In recent years, the unit storage cost of NAND Flash has rapidly decreased, leading to the widespread adoption of SSD (Solid State Drive) products. However, the P/E cycles of NAND Flash have also decreased due to the cost reduction efforts, and reducing the write traffic to NAND Flash can effectively extend its lifespan. This paper proposes a new buffer structure based on STT-MRAM with features such as byte addressing, low static power consumption, and non-volatility. By storing mapping tables, journals, and cached data in STT -MRAM, the persistence of data within the buffer is ensured. Combined with a journaling filesystem, a new write process is designed to guarantee the atomicity of the buffer, allowing for faster recovery from bootup or sudden power-off. Compared to DRAM, this solution reduces the write traffic caused by flush commands to permanently move data from the buffer to non-volatile areas, and decreases the capacitor requirements of PLP (Power Loss Protection) technology. It is estimated that this approach can increase the capacity of SSD products by 30%.