Convolution Acceleration Algorithm Address Generation Component Based on RISC-V

The convolution operation is a data-intensive algorithm that requires a lot of computing power. As convolutional neural networks become more complex, there are limitations to algorithmically accelerating convolution operations. The original architecture of general-purpose processors limits their efficiency in completing convolutional neural networks. Based on the RISC- V architecture, this article studies the address generation component of convolution operations, and proposes a multi-address generation component that can operate in parallel with ALU, including multiple addressing modes to support various convolution acceleration algorithms. Solve the problem of large amounts of data memory access taking up computing time in convolution acceleration algorithms. By comparing whether the address generation component is equipped under the RISC- V architecture, a benchmark test is performed to compare the instruction cycle cost. By further analyzing the cycle cost consumed in the convolution acceleration algorithm, the acceleration efficiency of the convolutional neural network by the address generation component based on the RISC- V architecture was obtained. Benchmark test results show that the address generation component equipped under the RISC- V architecture can save instruction cycle cost when executing convolution acceleration algorithms.