Integration and Verification of L1 Data Cache in SweRV EH1

RISC-V, an open-source instruction set architecture, has characteristics of high performance, modularity and easy expansion, therefore, numerous numbers of open-source cores have been employed in academic and commercial projects within a few years. Caches significantly boost CPU performance by storing frequently used data closer to the processor to reduce memory latency. This paper details our contribution to open-source hardware: integrating a parameterized set-associative Level 1 data cache with a Least Recently Used (LRU) replacement policy into the SweRV EH1 core, a widely used 32-bit RISC-V core. Supporting cache with a write-through policy and analysis of the hit/miss rate upon CPU requests. Design verification is done via standard and open-source verification tools.