An Energy-Efficient Edge Processor for Radar-Based Continuous Fall Detection Utilizing Mixed-Radix FFT and Updated Block-Wise Computation

In the scenarios of the Internet of Things, fall detection holds increasing significance in the health monitoring of elderly individuals. While most current research has achieved impressive performance in fall detection methods, there are limitations in deploying these methods to resource-limited edge devices. This paper proposes an energy-efficient edge processor for radar-based continuous fall detection, which consists of a preprocessing module and a convolutional neural network (NN) accelerator. Multiple designs were implemented to minimize resource utilization and power consumption of the entire processor: 1)A preprocessing module based on mixed-radix FFT is utilized for radar signal preprocessing. 2)An NN accelerator is designed to support an updated block-wise (UB-wise) computation technique aimed at reducing redundant calculations and intermediate result storage in continuous fall detection, along with a fully connected (FC) layer cache compression technique proposed to compress the cache required for FC layer computations. Applying these techniques results in an 80% reduction in RAM size, an 88.6% decrease in intermediate result storage, and a 92.6% reduction in multiply-accumulate operations. Implemented on an FPGA, this processor consumes merely 3.1k look up tables, 2.3k flip-flops, 4 block RAMs, and 7 DSPs while consuming only 0.234W of power. On an open-source radar-based fall detection dataset, the processor attains an accuracy of 98.58%. Additionally, it incurs a mere 42 us delay for a single preprocessing and NN inference, consuming just 9.8 uJ. Compared to state-of-the-art works, this processor’s energy consumption is reduced by 81.2%, and the required memory is reduced by 93.3%.