Optimizing Power Efficiency in SRAM Cells through Memristor-Based Architectures

Random Access Memory (RAM) cells find extensive applications in diverse digital electronic systems. In the realm of Static Random Access Memory (SRAM) cells, minimizing power consumption presents a formidable challenge, particularly in the context of ultra-low-power applications like implanted biomedical devices. Traditionally, the reduction of power consumption in Com-plementary Metal-Oxide-Semiconductor (CMOS) SRAM cells involves scaling down the supply voltage. However, this approach necessitates a concurrent scale-down of the process technology, impacting the read and write stability of the system. This research introduces a novel and expedient SRAM cell design comprising four transistors and four memristors (4T4M). Comparative analysis against conventional 6T and 4T2M SRAM cells demonstrates that the proposed 4T4M SRAM cell exhibits superior performance in terms of both power consumption and delay. All SRAM cells were meticulously modeled and simulated using 130nm technology in Cadence Virtuoso. The results indicate that the proposed 4T4M SRAM cell boasts a noteworthy reduction of 11.56% and 62% in power consumption when juxtaposed with 4T2M and 6T SRAM cells, respectively. Additionally, it demonstrates a faster response time, outperforming 4T2M and 6T SRAM cells by 10.5% and 57.5%, respectively.