Feedback Enhanced Area-Efficient ESD Power Clamp Circuit

In this article, a feedback-enhanced power clamp circuit for on-chip electrostatic discharge (ESD) protection is proposed and verified using silicon data. To conserve the layout area, the conventional MOSFET capacitor is replaced with a parasitic n-well/p-substrate junction capacitor to detect ESD events. The feedback mechanism is carefully designed to prolong the turn-on duration of the clamp circuit, thereby enhancing the ESD robustness. Experimental results show that the proposed clamp, featuring a
$2000~\mu $
m wide clamping MOSFET, achieves a comparable transmission line pulsing (TLP) failure current of approximately 9.5 A when compared to the conventional RC triggered counterparts. Simultaneously, it reduces the layout area, enhances false triggering immunity, and enhances the robustness during long pulse events.