Analysis of Leakage Mechanism in Irradiated 4H-SiC INV and NOR Logic Gate Circuits

The performance degradation of 4H-SiC CMOS devices, inverter (INV), and NOR logic gate circuits under irradiation are examined in this paper. It is noted that the leakage current of INV and NOR gate circuits is much higher than the summary leakage of NMOS and PMOS at a total irradiation dose of 300kGy, which indicates an extra leakage current path in INV and NOR gate circuits. The reason for leakage current is elucidated through Emission Microscope (EMMI) testing and analysis of leakage paths based on the layout. After irradiation, an inversion layer forms on the P-epi surface beneath the polysilicon gate and VDD metal, leading to electron leakage current from N-well to P-epi. At last, recommendations for enhancing the radiation tolerance of 4H-SiC CMOS gate circuits are proposed. Simulation verification using T -CAD tools has validated the effectiveness of this reinforcement method in substantially reducing both types of additional leakage.