Evidence of Dynamic Input Capacitance of SiC Power MOSFETs

This paper presents an evidence of dynamic input capacitance
$C_{\text{gg}}$
of SiC power MOSFETs. Based on the performed ramp-rate capacitance-voltage (C-V) measurements and circuit simulations, the dynamic
$C_{\text{gg}}$
behavior is explained by the distributed internal gate resistance defined by the on-chip gate layout network and the time-constant of charge trapping due to the present defects at the SiC-oxide interface. The ramp-rate-based
$C_{\text{gg}}-V_{\text{gs}}$
measurements with
$V_{\text{gs}}$
-ramp time of
$25\ \mu \mathrm{s}$
are compared with the standard
$C_{\text{gg}}-V_{\text{gs}}$
impedance analyzer (IA) measurements for a Si super-junction power MOSFET and two different SiC power MOSFETs. The differences between the ramp-rate- and the IA-based
$C_{\text{gg}}-V_{\text{gs}}$
measured curves are more significant for the two SiC power MOSFETs compared to the Si power MOSFET. This is attributed to SiC-oxide interface states and their time constant. The presented ramp-rate
$C_{\text{gg}}- V_{\text{gs}}$
measurement method should more accurately capture the actual C-V behavior during fast switching events.