Reducing turn-Off loss by suppressing Back-Side parasitic npn Transistor in Single-Back and Double-Front Gate-Controlled IGBT

Reducing turn-off loss
$(E_{\text{off}_{-}\text{total}})$
in insulated-gate bipolar transistors (IGBTs) improves the power consumption of high-power converter systems. Multi-gate IGBTs can reduce
$E_{\text{off}_{-}\text{total}}$
because stored carriers are reduced by adding independently controllable gates that switch just before the turn-off period. The single-back and double-front gate-controlled IGBT (SDG-IGBT) reduces
$E_{\text{off}_{-}\text{total}}$
when both the control gate (CG) on the emitter side and the back gate (BG) on the collector side are operated simultaneously. As the issue, a parasitic npn transistor on back-side decreases injection efficiency. The fabricated 4.5-kV class SDG-IGBT with deep p layer (DP) successfully decrease
$V_{\text{ce}(\text{sat})}$
by suppressing operation of a parasitic effects. Moreover, we clarify that the tradeoff between
$V_{\text{ce}(\text{sat})}$
and
$\Delta E_{\text{off}_{-}\text{total}}$
in mode-3 are improved because the storage carriers around BG is increased. In mode-2, The BG and CG can be redesigned individually, because the
$\Delta E_{\text{off}_{-}\text{total}}$
to mode-1 is almost the same between with and without DP. As the result, SDG-IGBT with DP achieves to reduce
$E_{\text{off}_{-}\text{total}}$
in mode-4.