Split-Gate CSTBT™ for Suppression of Negative Gate Capacitance Under Short Circuit

CSTBT™ can reduce on-state voltage drop
$(\mathrm{V}_{\text{CEsat}})$
by storing carriers. On the other hand, storing carriers causes flow of displacement current
$(\mathrm{I}_{\text{dis}})$
into the gate, resulting in the overshoot of the gate-emitter voltage (V
GE
). The phenomenon of IGBTs is expressed as a negative gate capacitance. In this study, we have found a solution to suppress the negative gate capacitance for
$\text{CSTBT}^{\text{TM}}$
, enabling the reduction in
$\mathrm{V}_{\text{CEsat}}$
by using a split-gate structure. Additionally, we have clarified the mechanism through a combination of measurements and device simulations. As a result, the split-gate achieved 76% reduction in integral of
$\mathrm{I}_{\text{dis}}$
at the same
$\mathrm{V}_{\text{CEsat}}$
compared to the conventional structure. This is because most of the
$\mathrm{I}_{\text{dis}}$
flowing to lower split gate is directed towards the emitter.