Gate Switching Instability of SiC MOSFETs under Simultaneously High Drain-Source Voltage and High Frequency Acceleration

SiC MOSFETs have recently been found to suffer from a prominent threshold voltage drift when applying an alter-nating voltage to the gate under certain conditions. In contrast to the well-known bias temperature instability (BTI), this newly observed degradation mechanism is dependent on the number of cy-cles performed and was termed gate switching instability (GSI). This paper presents the influence of an additional high electric field on gate reliability during GSI testing. Therefore, a new test concept is introduced where gate switching stress (GSS) is carried out, and simultaneously a high drain-source voltage is applied. The results of these frequency-accelerated tests on state-of-the-art SiC MOSFETs with different device technologies are shown and compared to non-high voltage GSS tests.